1. Field of Invention
This invention relates in general to a structure and a method of manufacturing a dynamic random-access-memory (DRAM) capacitor. More particularly, this invention relates to a structure and a method of manufacturing a stacked-type capacitor, as well as an improved combination of a stacked- and trench-type capacitor.
2. Description of Related Art
DRAM is a-type of volatile memory having a signal which is stored in a digital state, depending on the charging state of the capacitor, in each memory cell. FIG. 1 is a circuit diagram of a conventional DRAM cell, which comprises a metal-oxide-semiconductor (MOS) transistor 11 having a gate connected to a word line (WL). One end of a source/drain region is connected to a bit line (BL), while the other end of the source/drain region connected to ground via a capacitor 12. The digital signal of the DRAM cell is stored in the capacitor 12. The storage capacity for the digital signal increases with an increase in the charge stored in the capacitor 12. Furthermore, if the charge is increased, signal read out from the memory, using amplification circuits during a read operation, will be less affected by noise. For example, soft errors generated by .alpha.-particles will be greatly reduced.
There are several conventional methods of increasing the charge storage capacity of a capacitor. For example, by increasing the surface area of the conducting layer in the capacitor, or by reducing the thickness of the dielectric layer in the capacitor, the amount of charge capable of being stored in the capacitor can be increased. The stacked-type capacitor, as shown in FIGS. 2 through 4, is an example of a capacitor structure having an increased capacitor area.
FIG. 2 is a cross-sectional view of a conventional stacked-type DRAM capacitor structure. First, a semiconductor substrate 20 having a MOS transistor 22, a field oxide layer 26 and a conducting layer 27 formed thereabove, is provided. The MOS transistor 22 comprises a gate 23, source/drain regions 24 and spacers 25. Then, an insulating layer 28 is deposited. This is followed by etching the insulating layer 28 to form contact openings above designated source/drain regions 24. Thereafter, a lower electrode layer 29, a dielectric layer 210 and an upper electrode layer 211 are sequentially formed above the contact window. Lower electrode layer 29, dielectric layer 210 and upper electrode layer 211 form a stacked-type capacitor structure 212.
The dielectric layer 210 can be a silicon nitride/silicon oxide (NO) composite layer, or a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer. The lower electrode layer 29 and the upper electrode layer 211 can each be a polysilicon layer.
Finally, back-end processes, such as the formation of a metallic contact window 213 and the laying of a passivation layer (not shown in the figure), are performed to complete the fabrication of the DRAM structure.
FIG. 3 is a cross-sectional view of a second conventional stacked-type DRAM capacitor structure. First, a semiconductor substrate 30, having a MOS transistor 32, a field oxide layer 36 and a conducting layer 37 formed thereabove, is provided. The MOS transistor 32 is comprised of a gate 33, source/drain regions 34 and spacers 35. Then, an insulating layer 38 is deposited. This is followed by etching the insulating layer 38 to form contact openings above designated source/drain regions 34. Thereafter, a lower electrode layer 39, a dielectric layer 310 and an upper electrode layer 311 are sequentially formed above the contact window. Lower electrode layer 39, dielectric layer 310 and upper electrode layer 311 together form a stacked-type capacitor structure 312.
The dielectric layer 310 can be a silicon nitride/silicon oxide (NO) composite layer or a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer. The lower electrode layer 39 and the upper electrode layer 311 can each be a polysilicon layer. Additionally, the lower electrode layer 39 has an irregular up-and-down surface profile.
Finally, back-end processes, such as the formation of a metallic contact window 313 and the laying of passivation layer (not shown in the figure), are performed to complete the fabrication of the DRAM structure.
FIG. 4 is a cross-sectional view of a third conventional stacked-type DRAM capacitor structure. First, a semiconductor substrate 40, having a MOS transistor 42, a field oxide layer 46 and a conducting layer 47 formed thereabove, is provided. The MOS transistor 42 is comprised of a gate 43, source/drain regions 44 and spacers 45. Then, an insulating layer 48 is deposited. This is followed by etching the insulating layer 48 to form contact openings above designated source/drain regions 44. Thereafter, a lower electrode layer 49, a dielectric layer 410 and an upper electrode layer 411 are sequentially formed above the contact window. Lower electrode layer 49, dielectric layer 410 and upper electrode layer 411 together form a stacked-type capacitor structure 412.
The dielectric layer 410 can be a silicon nitride/silicon oxide (NO) composite layer or a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer. The lower electrode layer 49 and the upper electrode layer 411 can each be a polysilicon layer. Additionally, the lower electrode layer 49 has an undulating surface profile to increase the surface area of the capacitor structure 412.
Finally, back-end processes, such as the formation of a metallic contact window 413 and the laying of a passivation layer (not shown in the figure), are performed to complete the fabrication of the DRAM structure.
The aforementioned stacked-type capacitor structures are currently the most common capacitor structures for DRAMs in use. These conventional methods all rely on improving the surface morphology of capacitors. Although the increase in surface area of the capacitor obtained by such methods increases its capacitance, the amount of such increase is limited, and is ineffective when applied to small dimensional components.